TIMING Module Documentation
This module is responsible for generating trigger pulses / strobes for the application from various input sources. Each trigger channel can be sourced in four different ways.
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Input clock of the TIMING module
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Manual trigger from the PCIe register (eg. using QtHardMon)
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External trigger sources (eg. Backplane MLVDS Lines or Harlink Connector on SIS8300L2 or Whiterabbit signal)
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Loopback → The users can route one of the generated trigger channels as an input source to any other trigger channel After the source is selected user can define a division value to reduce the frequency of the trigger channel
Each trigger channel can be further delayed. Delay value corresponds to the number of clock cycles. Users can select either to use the normal trigger channel or the delayed version of it on run-time.
Each generated channel can later be synchronized to the following sources: (Reset the counter value so the phase is fixed to a particular channel)
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No sync (Free running counter)
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One of the generated triggers (loopback)
There are no synchronizers for the external trigger inputs for TIMING module. This means external triggers must be already synchronized to application clock domain. Each external trigger (also manual trigger) goes through edge detector to have reliable source.
1. Register Descriptions
Most of the registers lengths gets configured through how many trigger outputs are configured for the Timing Module. (determined by a constant C_TRG_CNT). This parameters currently gets fetched through appconfig.
| Name | Register Width | Number of Elements | RO/RW | Description |
|---|---|---|---|---|
ID |
32 |
1 |
RO |
LSB 8 bits shows number of output channels, next LSB 8 bits shows the number of external trigger channels that TIMING module is configured for |
VERSION |
32 |
1 |
RO |
Shows the git revision number |
ENABLE |
C_TRG_CNT |
1 |
RW |
Enable the output of the particular trigger channel |
SOURCE_SEL |
8 |
C_TRG_CNT |
RW |
Select the source for trigger generation. These numbers are application dependent. e.g. Single Cavity Regulation (7 Trigger channels with 8 external trigger sources, values are an integer!) 0 ⇒ Use Application Clock |
SYNC_SEL |
8 |
C_TRG_CNT |
RW |
Select synchronization input for the particular trigger channel 0 ⇒ No synchronization (Free running) |
DIVIDER_VALUE |
32 |
C_TRG_CNT |
RW |
Divider value for the particular trigger channel. eg. If you want to divide by 2 write 1 |
TRIGGER_CNT |
32 |
C_TRG_CNT |
RO |
Counter for each generated trigger channel ( (!) It counts even if the output is disabled (!) ) |
EXT_TRIGGER_CNT |
32 |
C_TRG_CNT |
RO |
Counter for each external trigger coming into the Timing Module ( (!) Gets effected by WORD_DIVIDER_VALUE (!) ) |
DELAY_ENABLE |
C_TRG_CNT |
1 |
RW |
Enables the delayed version for that particular trigger channel |
DELAY_VALUE |
32 |
C_TRG_CNT |
RW |
Delay value for that particular trigger channel |
MANUAL_TRG |
1 |
C_TRG_CNT |
RW |
Manually triggering a particular trigger channel. Writing 1 to a particular channel will trigger that channel once. (If the divider is set to 0) … |
2. Known Issues
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TIMING module can only produce maximum 32 trigger channels. This is because limitation with the address space. If any user requests this please contact firmware team.
3. HDL Dependencies
The Timing Module depends on the following packages:
Registers are generated using DesyRDL. (pypi.org/project/desyrdl/)