bsp_fmc2zup Module Documentation

The DAMC-FMC2ZUP (aka. Super-Carrier, or simply ZUP) is a high-end FMC/FMC+ carrier in MTCA.4 form factor based on the ZU11EG FPGA, part of Xilinx ZYNQ Ultrascale+ MPSoC portfolio.

The card provides two FMC sockets, one FMC+ (VITA 57.4 compliant) and one FMC High Pin Count (VITA 57.1 compliant), with fully populated LA and HA differential pair groups and can operate on VADJ level from 1.2V to 1.8V. 24 MGTs are available to the FMC+ and 8 to the FMC HPC.

The board provides extensive backplane connectivity and all ports defined by standard are accessible from FPGA firmware/software. The embedded ARM Cortex-A53 Quad-Core and Cortex-R5 Dual-Core processors available in the MPSoC FPGA support running a Linux OS, either from a MicroSD card accessible from the front panel or from an embedded 8GB eMMC flash memory. The Processing System has 4GB of dedicated DDR memory, can store data on SATA devices through ports 2 and 3 (requires additional SATA storage AMC) and can be accessed from the network through the MTCA backplane port 0. Front panel USB type-C connector provides USB2, USB3 and DisplayPort connectivity using an external USB-C Hub/Dongle.

Flexible Clocking Scheme with White Rabbit support provides capability to receive and distribute clocks over the backplane and from the front panel high density connector.

The RTM interface is designed according to class D1.1 and carries full 42 LVDS lines and 2 MGT links. Zone 3 pins are handled through Spartan 7 FPGA. The board supports all existing digital RTMs from DESY, such as DRTM-AD84,DRTM-VM2, DRTM-PZT4.